Purdue University Graduate School

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posted on 2023-07-26, 15:17 authored by Donghyun SeoDonghyun Seo

 With the increased use of the internet, artificial intelligence, IoT, and wearable devices, it has become significantly critical to ensure security and confidentiality of information, particularly within these resource-constrained edge devices. The increased attentions to security and confidentially of information led to the development of computationally-secure cryptographic algorithms. At the same time, low-power sensing devices have emerged as highly promising tools for a wide range of technological applications such as diagnostics, physiological monitoring, and healthcare systems. The desire for seamless and continuous monitoring in sensing applications necessitates these devices to be compact in size and exhibit low power consumption, making them suitable for wearable or portable use with batterypowered operation.

 Keeping this objective in focus, I will structure this dissertation into the subsequent chapters. The first part (Chapter 2) will cover a theoretical analysis of the proposed Co-planar capacitivE Asymmetry SEnsing (CEASE) technique utilizing four on-die top-layer metal plates. Also, it will present the comparison with other sensing methods which are capacitive parallel and inductive sensing technique in terms of detection range through electromagnetic simulation. The second part (Chapters 3) of this this dissertation will involve explore of the concept of capacitive sensing in an IC layout and co-optimizing both the ground plane capacitance and the sensing capacitance to maximize sensitivity. It will present design of the post-processing circuits and systems with ultra-low power for sensing attacks and to prove the efficacy through the post-layout simulation results. Additionally, integration with digital SCA protection and AES-256 crypto core and checking the efficacy of the proposed method using the integrated detection and countermeasure system in post-layout simulations. Next in Chapter 4, we will show the lowest-power and the energy/conversion step time-based RDC for low frequency applications. It will presents the ways to enhance the energy-resolution trade-offs in time-based RDC, improving the rms jitter/phase noise with help of speed-up latches, to achieve higher bit-resolution. Furthermore, the power/performance trade-off in experiment through 3 different design variations optimized towards lowest energy baseline, higher resolution, and process portability tapeout and IC measurements is presented. Finally, in Chapter 5, we will show a novel proposed switchable dual-mode device that combines a high-frequency antenna and a Human Body Communication (HBC) coupler in a single device. The integration of these two modes addresses the limitations of HBC, such as restricted data transmission, and overcomes the drawbacks of signal absorption in the 24GHz frequency band by the human body. 


Degree Type

  • Doctor of Philosophy


  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Shreyas Sen

Additional Committee Member 2

Kaushik Roy

Additional Committee Member 3

Saeed Mohammadi

Additional Committee Member 4

Byunghoo Jung

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