Purdue University Graduate School
Dissertation - Atomically Thin Indium Oxide Transistors for Back-end-of-line Applications.pdf (3.94 MB)

Atomically Thin Indium Oxide Transistors for Back-end-of-line Applications

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posted on 2022-06-14, 17:43 authored by Adam R CharnasAdam R Charnas

As  thefundamentallimits  of  two-dimensional(2D)geometric  scaling  of  commercial transistors  are  being reached,  there  is  tremendous  demand  for  new  materials  and  process innovations  that  can  keep  delivering  performance  improvements  for  future  generations  of computing chips. One major avenue being explored istheincorporation ofan increasing degree of three-dimensionality   by   vertically   stacking   logic   and   memory   layerswith   high-density interconnections.In  this  dissertation,  high-performanceultra-thin  amorphousindium  oxide transistors  are  demonstrated as  an  excellent  candidate  for these  back-end-of-line  (BEOL)  and monolithic 3D (M3D) integration applications.

A  major  pain-point  in the  development  of  BEOL  and  M3D  systems is  the  strict  thermal budget imposed –once the bottom layer of devices is fabricated, they can generally withstand no more  than  400 °C.  It  is  exceedingly  difficult  to  directly  deposit  single-crystal  material  at  these temperatures, and polycrystalline materials will have grain boundary instability issues. Amorphous materials  generally  have  low  carrier  mobilities,  which  would  seemingly  remove  them  from contention as well. Indium oxideand itsclass of related metal oxides are exceptions. Indium oxideis  a  wide  bandgap  semiconductor  with  high  electron  mobility  up  to  about  100  cm2/V∙s  in amorphous form. Ithas a strong preference for native degenerate n-type doping which has hindered prior  devices  fabricated  with it.  In  this  dissertation,  extremely  thin  layers  on  the  order  of  1  nm thick are used for which quantum confinement effects widen the bandgap further, reliably enabling gate-controllable  carrier  densitiesand  demonstration  of  excellent  transistor  performance  with  a low thermal budget of just 225 °C.

Detailed characterization is performed down to 40 nm channel lengths revealing excellent transistor characteristics  includingenhancement-mode operation withon currents greater than 2 A/μm, low  subthreshold  swing,and  high  on/off  ratios  due  to  the  wide  bandgap.  Subsequent chaptersdemonstrate the fundamental lower limits of off current around 6 ×10-20 A/μmby a novel measurement  technique,  good  gate  bias  stress  stability  behaviorwith  small  parameter  drift  at silicon  complementary  metal  oxide  semiconductor  (CMOS)  logic  voltages,  and  high-frequency operationin the GHz regime enabling easy operation at CMOS clock frequencies.


Degree Type

  • Doctor of Philosophy


  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Peide Ye

Additional Committee Member 2

Dmitry Zemlyanov

Additional Committee Member 3

Wenzhuo Wu

Additional Committee Member 4

Haiyan Wang

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