DEVICE-CIRCUIT CO-DESIGN OF MULTI-DOMAIN HZO-BASED FERROELECTRIC METAL FIELD EFFECT TRANSISTORS

Since the discovery of ferroelectricity in CMOS-compatible Hafnium dioxide, ferroelectric-based non-volatile memories have been explored extensively as a next-generation memory technology. Amongst various ferroelectric-based memories, Ferroelectric Metal Field effect transistors (FeMFETs - with a ferroelectric and metal layer integrated into the gate stack) have shown immense promise. Compared to traditional non-volatile storage devices, FeMFETs have low operating voltages and hence low power consumption. However, FeMFETs have certain limitations, such as charge leakage through the floating internal metal layer (IML) between the gate dielectric and ferroelectric, which affects the sense margin over long periods of time. To address such limitations, a variant of this device was explored in the past, considering single-domain ferroelectric characteristics, which is a reconfigurable FeMFET. It has many advantages over conventional FeMFETs, such as the dynamic reconfigurability of polarization hysteresis and reduced energy consumption. Yet another variant utilizes a transistor controlling the internal metal layer potential to mitigate the charge leakage issues of FEMFETs, which is a 2T-1C FeMFET. While several flavors of FEMFETs have their own advantages and disadvantages, a comprehensive comparison is limited. In our work, we extensively explore and analyze the different flavors of FeMFETs to mitigate the abovementioned limitations considering multi-domain HZO ferroelectric material. Firstly, we observe that multi-domain R-FeMFETs can achieve dynamic reconfigurability and performance benefits for memory applications as shown in the previously reported single-domain approximation; they suffer from similar limitations as FeMFETs (that is, charge leakage through the internal metal layer) and reduced distinguishability (current ratio ∼3.5) due to the multi-domain minor loop characteristics of ferroelectric material. We apply read schemes that can mitigate the issues arising from charge leakage. We explore another variant of FeMFET, which is a 3T-1C FeMFET memory cell, where the access transistor is directly connected to the IML. This results in direct control of IML and overcomes the drawback of charge leakage in FeMFETs/R-FeMFETs. This cell has certain benefits, such as a very low write voltage of ∼2V compared to FeMFET for the comparable size of the transistor. We show that 3T-1C can achieve a single-cycle write scheme and improved read sense margin compared to R-FeMFET (current ratio > 7). We then compared the different FeMFET-based memory cells for performance analysis. Considering iso-switching time during a write and iso-pre-charging time during a read, the 3T-1C has an energy reduction of at least 43% and 67% in write and read, respectively. Read energy is the lowest amongst the different FeMFET bit-cells in the 3T-1C cell. R?FeMFETs exhibit the lowest write energy with an energy reduction of 59%, and read energy reduction is 60% compared to the existing FeMFET-based memory cells. Considering the different write and read schemes, read latency in R-FeMFET is the lowest, and write latency in 3T-1C FeMFET is the lowest