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posted on 2023-07-14, 20:02 authored by Karam ChoKaram Cho

        The last decade has witnessed an explosive growth in highly data-centric applications such as Internet of Things (IoT) and Artificial Intelligence (AI). Such applications demand highly efficient data storage and processing, especially when the systems operate under high energy/resource constraints, such as in intermittent-powered systems or edge AI platforms. Therefore, at the hardware level, high storage capacity along with low power operations has become more crucial than ever. Although conventional silicon-based complementary metal-oxide semiconductor (CMOS) has brought great prosperity to the semiconductor industry to date, enabling high-performance computing, increasing leakage energy and low cell density hinder their ability to sustain their benefits at scaled nodes and meet the demands of emerging data-intensive workloads. On the other hand, emerging non-volatile memories (NVMs) have gained much attention due to their distinct advantages over CMOS, such as zero leakage, high density, and non-volatility. However, they suffer from issues associated with high write power, endurance and/or variability. Thus, there is a need for new memory technologies that offer high density, low power and high-performance attributes to meet the data storage and efficiency demands of the new workloads. Furthermore, such technological advances need to be supported by architectural innovations. Despite hardware advances, the energy efficiency gains in traditional von-Neumann architectures are limited by power-hungry data movements between memory and processor, also known as the memory bottleneck. To alleviate this issue, in-memory computing (IMC) has emerged as a promising technique, wherein certain computations are executed within a memory macro, thus reducing processor-memory transactions. Along similar lines, incorporating non-volatile storage in logic state elements, such as flip-flops, has gained much attention for intermittently-powered systems, wherein the state of the processor is efficiently backed-up in the local non-volatile memory in the event of a power failure. Such techniques enabling logic-memory synergy reduce compute, storage, and/or communication costs and thus can be highly promising for future computing platforms. However, existing techniques for logic-memory fusion suffer from key design bottlenecks that need to be mitigated via extensive technology-circuit-architecture co-design. In this dissertation, we address some of the issues associated with data storage and processing by exploring spin-based low-power non-volatile devices, their memory applications, and logic-memory coupling enabled by their unique technological attributes. 

      We propose spin-based devices that employ the valley-spin Hall (VSH) effect in monolayer transition metal dichalcogenides (TMDs), such as tungsten di-selenide (WSe2). With the unique features of WSe2, the proposed devices are designed to have an integrated back-gate, enabling control of the charge and spin currents in 2D TMD channel. This design leads to an access-transistor-less compact layout in memory arrays. The generated spin currents diverge into opposite directions with out-of-plane spins, allowing for the coupling of WSe2 with perpendicular magnetic anisotropy (PMA) magnets. This enables low-power write operations and facilitates differential logic encoding within a single device. Additionally, we utilize inter-layer exchange-coupling mediated by FeCo-oxide and Ta layers to electrically isolate but magnetically couple the PMA free layers. This configuration benefits read performance by achieving low series resistance in the read path. To ensure reliable inter-layer coupling and the functionality of the proposed devices, we perform micromagnetic OOMMF simulations and extensively investigate the impact of process variations on the exchange-coupled PMA free layers. From the simulations, we conclude that the proposed design is resilient to potential process variations arising from misalignment of the PMA free layers and reductions in exchange-coupling strength. Based on the proposed devices, we explore circuit designs for logic and memory applications. 

      First, we propose VSH effect-based non-volatile flip-flops (VSH-NVFFs) using the proposed devices to introduce non-volatility in logic targeted for intermittently powered systems. The key challenge to design such systems is to enable energy-efficient data back-up in the event of power failure. In our design, we achieve high energy-efficiency via device-circuit co-design of VSH devices and NVFFs. We propose two flavors of NVFFs: NVFF-1 with a compact design and NVFF-2 targeted for lowering data restore energy. Compared to existing giant spin Hall (GSH) effect-based NVFFs, also known as spin-orbit torque or SOT-NVFFs, our NVFFs exhibit 68%-71%, 74%-75% and 55%-59% lower normal, back-up, and restore energies, respectively. Among the proposed VSH-NVFFs, NVFF-1 exhibits 8% lower operation energy than NVFF-2, while NVFF-2 exhibits 6% lower back-up energy and 11% lower restore energy. This result suggests that NVFF-1 is more suitable for systems with a smaller number of checkpointing operations (data back-up/restore), while NVFF-2 is beneficial for systems needing a larger number of checkpointing operations. Furthermore, by conducting Monte Carlo simulations, we confirm the reliable restore operation of the proposed NVFFs.

      Secondly, we design memory arrays using the proposed devices to gain benefits over previously proposed VSH effect-based memory designs, in which read currents flow through a highly resistive 2D TMD channel, degrading read performance. For read operations, our memory array requires a read access transistor. By sharing the read access transistor per word, we minimize the area overhead in our memory array design. The area of our bit-cell is comparable to a previously proposed VSH memory, despite the inclusion of an additional read access transistor. Additionally, with the electrical isolation of the read and write paths in our design, we achieve improvements in read performance, with reductions of 39%-42% and 36%-46% in read time and energy, respectively. However, this improvement comes at the cost of write performance, with a 1.7X and 2.0X increase in write time and energy, respectively. We also achieve a 1.1X-1.3X larger sense margin (SM) and a 1.2X-1.3X improvement in read disturb margin (RDM). Furthermore, by increasing the size of the read access transistor in our memory array, we can further improve the SM by up to 1.5X-1.6X with only a 7%-12% area increase. Our design can be particularly useful for applications that involve frequent reads and few writes, such as neural accelerators.

      We further expand our exploration of VSH effect-based devices for implementing IMC. As XNOR-based binary neural networks (BNNs) have shown immense promise for resource-intensive AI edge systems, their implementation has been explored using SRAMs and emerging NVMs. However, these designs typically need two bit-cells (2T-2R) to encode signed weights, resulting in an area overhead. Therefore, we address this issue by proposing a compact and low-power IMC technique for XNOR-based dot products. Our approach utilizes the VSH effect in monolayer WSe2 to design XNOR bit-cells that feature an access-transistor-less compact layout and differential weight encoding in a single device (XNOR-VSH). We co-optimize the proposed VSH device and the memory arrays to enable efficient in-memory dot product computations between signed binary inputs and signed binary weights. The compactness of the proposed XNOR-VSH array leads to 4.8%-9.0% lower compute latency and 36.6%-62.5% lower compute energy, along with 49.3%-64.4% smaller area compared to spin-transfer torque magnetic RAM (STT-MRAM) and SOT-MRAM based XNOR-arrays.

      Lastly, we explore the modeling and design of voltage-controlled spintronic devices, which have shown remarkable potential for ultra-low-power and high-speed operation empowered by magnetoelectric (ME) materials. The proposed ME device utilizes a monolayer WSe2 channel placed on top of a Cr2O3 ME dielectric, which are electrostatically controlled by top and bottom gates. To capture the electrostatics in 2D TMD and the gate-voltage-dependent ME effect, we establish a modeling framework using a distributed capacitive network. This framework self-consistently accounts for the interactions between the various components. We verify the functionality of the proposed model by simulating the proposed device, and show how it can capture the device characteristics.


Degree Type

  • Doctor of Philosophy


  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Sumeet Kumar Gupta

Additional Committee Member 2

Kaushik Roy

Additional Committee Member 3

Zhihong Chen

Additional Committee Member 4

Pramey Upadhyaya

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