Low Dimension Materials for Extend/Beyond CMOS Applications
2-dimensional
layered materials, transition metal dichalcogenides (TMDs) are considered
promising candidates for the post-Si era. They have attracted wide attention
from both fundamental and applied research communities, owing to their unique
material properties and potential applications including logic and memory
devices. The key reason that TMD materials are excellent channel material
choices for logic devices is that their inherent layered-structures allowing
uniform thickness control with atomic-level precision and can reach the ultimate
monolayer thickness limit of ~ 0.7nm, which is desirable for the implementation
of ultra-scaled devices to maintain excellent electrostatic control.
In this
thesis, I will first focus on a unique contact gating on TMD-based
Schottky-barrier transistors and discuss in great detail the impacts of current
injection from source/drain contacts to channel regions in a typical back-gated
structure. I will reveal a commonly observed overestimation of TMD mobility
when substantially large contact resistance has a strong gate dependence, and
suggest that an appropriate method is necessary for precise mobility
extraction. For extending CMOS beyond Si, various extrinsic doping schemes are
investigated to achieve a much-reduced contact resistance (RC) on tungsten
diselenide (WSe2) which is associated with the Schottky-barrier
height. Devices implemented on ultra-thin gate dielectric are then explored on tungsten
disulfide (WS2) with various TMD body thicknesses (TCH),
with an excellent off-state behavior and on-state performance being achieved on
properly selected TCH based on our statistics. The observed
ultra-low RC and record-high on-state current at a much-scaled
overdrive (VOV) highlights the advantages and necessities of exploiting
ultra-thin gate dielectric on TMD-based electronics.
The
second part of the thesis focuses on beyond CMOS applications including
reconfigurable logics and tunneling field-effect transistors (TFET). Owing to
ultra-thin TCH in low dimensional materials, the triple-gate design
allows efficient electrostatic control on WSe2 and carbon nanotube
(CNT) by creating various doping types and concentrations within different
channel segments. Therefore, a single triple-gate device can operate as a metal
oxide semiconductor field-effect transistor (MOSFET), a TFET, or a diode
depending on the choice of the gate biases. In the TFET mode, a steep
subthreshold slope less than 60 mV/dec has been achieved in the CNT devices at
room temperature. To extend the applications from device to circuits, the
capability of modulating the device on-state performance is utilized in a WSe2
CMOS-based inverter and static random access memory (SRAM) design to improve
the read and write stability and achieve a low voltage operation.
Funding
Semiconductor Research Corporation
History
Degree Type
- Doctor of Philosophy
Department
- Electrical and Computer Engineering
Campus location
- West Lafayette