Purdue University Graduate School
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posted on 2020-12-11, 19:50 authored by Avinash YadavAvinash Yadav
In the era of high-speed circuits and systems, CMOS technology has reached its limits. The balance of power, performance, and area trade-off is the base of current digital systems. Industries are designing chips at the cutting-edge technologies using 3nm, 5nm, 7nm, and 10nm processes. These advanced node technologies allow to efficiently direct the flow of electrons making the high-performance low-power devices physically possible. The aforementioned Power Performance Area (PPA) trade-off varies significantly for different applications. Moreover, semiconductor device parameters vary with the process and environmental variations that are modeled under term Process, Voltage, and Temperature (PVT). A satisfactory PVT operating conditions ensure the good behavior of the circuit for the desired application.

In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings. The FinFET technology was chosen since it has a subthreshold slope of 60mV/decade that enables cells to function at 0.7V supply voltage at the nominal corner. An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device. An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness.

The 7nm FinFET device was then employed into 6T SRAM cells and 16 function ALU. The SRAM cells were approached with advanced multi-corner stability evaluation. The system-level architecture of the ALU has demonstrated an ultra-low power system operating at 1 GHz clock frequency. The ALU design introduces an Intellectual Property (IP) characterized by different PVT corners suitable for Low power, machine learning, embedded systems, and other complex computer arithmetic applications. Each of the circuit and system represents significant speedup over planar CMOS technologies and contributes to the field of Ultra Large Scale of Integrated Circuit (ULSI) design.

The 7 nm FinFET device explored as the minimum threshold voltage of 207mV, maximum effective current of 18.26 µA, and maximum power consumption of 14.75 µW with high speed measured via multi-corner simulation. A comparative study between the various advanced technologies was introduced to designate the unique features of the FinFET system technology.

The successful design and simulation of the SRAM cells led to a robust design for the L2/L3 caches that may feature high-performance microprocessors. A complete FinFET CPU integrating more instructions is reserved for future considerations.


Degree Type

  • Master of Science in Electrical and Computer Engineering


  • Electrical and Computer Engineering

Campus location

  • Indianapolis

Advisor/Supervisor/Committee Chair

Dr. Maher E. Rizkalla

Additional Committee Member 2

Dr. Trond Ytterdal

Additional Committee Member 3

Dr. John J. Lee