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Passive Mitigation of Common-Mode Current in Three-Phase Two-Level Inverter-Based Systems

thesis
posted on 30.07.2021, 02:47 by Harshita SinghHarshita Singh
Power electronic converters are being used in a variety of applications, from electric vehicles to the utility grid. These converters are designed to offer high efficiency, which is achieved by switching semiconductor devices between on or off states at a high frequency. Associated with this switching is a common-mode voltage. The high-frequency components in this voltage excite the parasitic capacitances in the system, resulting in the flow of common-mode current. Since this current completes its path through an unintended path, it can interfere with the functioning of other devices or equipment. One way to reduce the CM current in a system is through the use of passive components. These include strategically placed capacitors and common-mode inductors to limit the impact of the common-mode quantities.

While the design of common-mode inductors has been set forth in the literature, the effect of magnetic hysteresis in the core has been inappropriately ignored. This phenomenon becomes increasingly important when the allowable common-mode current is significantly smaller than the differential-mode current, such as in high-power converters.

In this work, passive mitigation of common-mode current in three-phase two-level voltage-source-inverter based systems is considered. A mitigation strategy is proposed and described. The components used in this strategy, namely a common-mode inductor and a proposed common-mode shorting network, are introduced. This is followed by a discussion on the time domain hysteresis modeling that facilitates the magnetic design of a common-mode inductor. The issue of self-capacitance of a common-mode inductor is then addressed. Then, a rigorous multi-objective optimization-based design methodology for a common-mode inductor which addresses magnetic hysteresis at a fundamental level is set forth.

This is followed by a discussion of a new tool in common-mode current mitigation, a proposed common-mode shorting network. A design strategy for this component is also set forth. The dissertation concludes with two experimental system demonstrations of the proposed strategy and components on laboratory test systems.

History

Degree Type

Doctor of Philosophy

Department

Electrical and Computer Engineering

Campus location

West Lafayette

Advisor/Supervisor/Committee Chair

Scott Sudhoff

Additional Committee Member 2

Dan Jiao

Additional Committee Member 3

Steven Pekarek

Additional Committee Member 4

Oleg Wasynczuk

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