Purdue University Graduate School
Dissertation_v5_Chiang_07292022.pdf (7.7 MB)


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posted on 2022-07-29, 19:52 authored by Chin Cheng ChiangChin Cheng Chiang


Future artificial intelligence applications and data-intensive computations require the development of non-von Neumann architecture. Physical separation between a logic unit and a memory unit is one of the main bottlenecks of the traditional architecture, hindering unlocking the ultimate performance of electronic devices, such as power consumption and memory bandwidth limitation. However, to enable monolithic integration of high-performance logic and memory needs to resolve the fundamental thermal budget challenge of back-end-of-line (BEOL). In this regard, two-dimensional (2D) materials have drawn immense attention owing to their intrinsic performance, ultrathin bodies, and flexibility. The viability of low-temperature integration puts them in an advantageous position that rivals silicon technology.

Firstly, an entirely new phase change RRAM in MoTe2 can give rise to uniform switching by difference from a random filament formation of the conventional RRAM device. For a large memory array to function properly, it is crucial to have high nonlinearity of I-V characteristics for each device to suppress the sneak-path current. I experimentally demonstrate a proof-of-concept heterostructure consisting of 2D materials with the functionalities of the memory (MoTe2) and selector (WSe2). Next, a heterogeneously integrated 1-selector/1-resistor (1S1R) Ta2O5/MoTe2 RRAM cell was built for the first time employing 2D layered MoTe2 films, showing decent on/off-current ratios of ~730 and high nonlinearities of ∼5700. These values are considered state-of-the-art for built-in nonlinear RRAM devices to date. 

Secondly, I demonstrate that a pure nitric oxide treatment at elevated temperatures provides a stable p-doping for monolayer WSe2. This approach allows achieving record high hole current densities of ~300 μA/μm and low contact resistances of ∼950 Ω·μm, while preserving the transistor on/off current ratio >2×106. This scalable pathway significantly improves the performance of p-type WSe2 transistors, opening new opportunities for p-type 2D materials to enable CMOS implementations for next-generation high-performance electronics. 

Thirdly, I demonstrate all MoTe2 1-transistor/1-resistor (1T1R) memory cells, fabricated at low temperatures. The 1T1R cells can be switched with voltage ~ 1V, close to typical CMOS logic voltages. This demonstration underscores the potential of 2D materials and their monolithic integration toward the realization of future memory technologies. 

Lastly, I adopt machine-learning (ML) algorithms to evaluate the design and process co-optimization from a vast number of 2D transistor device characteristics. This framework greatly optimizes the electrical performance of 2D transistors, serving as guidance for advancing future 2D electronics.


Degree Type

  • Doctor of Philosophy


  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Zhihong Chen

Additional Committee Member 2

Vladimir Shalaev

Additional Committee Member 3

Peide Ye

Additional Committee Member 4

Joerg Appenzeller

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