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Storage-Aware Test Sets for Defect Detection and Diagnosis

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posted on 2024-04-03, 12:37 authored by Hari Narayana AddepalliHari Narayana Addepalli

Technological advancements in the semiconductor industry have led to the development of fast, low-power, and high-performance electronic devices. With evolving process technologies, the size of an electronic device has greatly reduced, and the number of features a single device can support has steadily increased. To achieve this, billions of transistors are integrated into small electronic chips leading to an increase in the complexity of manufacturing processes. Electronic chips that are manufactured using such complex manufacturing processes are prone to have a large number of defects that are difficult to test, and cause reliability issues. To tackle these issues and produce highly reliable chips, there is a growing need to test each manufactured chip thoroughly. This requires the application of a large number of tests by a tester. The cost of testing an electronic chip primarily depends on the storage requirements of the tester, and the test application time required. The large number of tests required to rigorously test each chip leads to an increase in the testing cost. Earlier works reduced the testing cost by reducing the input storage requirements of the tester. The input storage requirements are reduced by using each stored test on the tester to apply several different tests to the circuit. Several different tests are also applied based on each stored test to improve the quality of a test set. The goal of this thesis is to aide in producing reliable chips, by creating test sets that can detect faults from different fault models. The test sets are created by improving the quality of a test set.


First, test sets with low storage requirements are produced for defect detection. A base test set is generated and stored. Each stored test is perturbed to produce several different tests. Algorithms are then described in two different scenarios to select a subset of the perturbed tests. The selected subset of tests improves the quality of defect detection with a minimal increase in the input storage requirements.


Next, test sets with low-storage requirements are produced for defect diagnosis. A fault detection test set is generated and stored. Each stored test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests to be used as diagnostic tests. The diagnostic test set selected improves the quality of defect diagnosis with a minimal increase in the input storage requirements.


Finally, storage-aware test sets are produced targeting several fault models in two steps. In the first step, tests in a base test set are replaced with improved tests to produce an improved test set. The improved test set is stored, and it improves the quality of defect detection with no increase in the storage requirements. In the second step, each improved test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests. The selected subset of tests further improves the quality of defect detection with a minimal increase in the input storage requirements.

Funding

Semiconductor Research Corporation 2020-CT-2967

History

Degree Type

  • Doctor of Philosophy

Department

  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Irith Pomeranz

Additional Committee Member 2

Sumeet Kumar Gupta

Additional Committee Member 3

Timothy G. Rogers

Additional Committee Member 4

Anand Raghunathan

Additional Committee Member 5

Byunghoo Jung

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