Purdue University Graduate School
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posted on 2021-04-30, 16:32 authored by Ruiping ZhouRuiping Zhou

The miniaturization of a MOSFET is the constant driving force in semiconductor technology over the decades. This scaling enables the realization of the ever complex and functional integration on a single chip where over tens of billions of transistors densely packed. Silicon (Si) is always the golden performer until recent years when the shrinking of a transistor becomes more and more difficult, due to phenomena such as short channel effect and mobility degradation, which is a challenge especially for atomic level scaling. The dawning of low dimensional materials, such as graphene, transition metal dichalcogenides (TMDs), black phosphorus (BP), with their natural atomically thin two-dimension (2D) layered structure and other novel properties, might serve as an alternative solution for ultimate scaling. However, the understanding of the electronic transport in these Van der Waals materials is still lacking.

In this research, the exploration of this material was first initiated on the vertical heterojunctions where two materials’ interfaces meet. Many previous literatures claimed this hetero-interface creates a P/N junction that results in a diode-like rectification. Yet, by careful analysis and comparing with our “real” vertical structures where the lateral components were eliminated, it is proved this rectification is a direct result from the contact region. The Schottky barrier on the drain side together with the gate effect is the true culprit.

Realizing how the Schottky barrier could be dominating in these 2D FETs, the second study is the Schottky barrier effect on the contact resistances and furthermore the mobility of the device. Because of the existence of the Schottky barrier between the channel and contact, the contact resistance is not negligible, unlike the ohmic contact for conventional Si MOSFETs. By comparing the intrinsic and extrinsic mobilities of TMD materials, It is found that the contact resistance’s response to the back gate, namely, the rate of how it changes with the back gate has a huge factor in determining whether the extrinsic field-effect mobility underestimates or overestimates its intrinsic mobility. This opens a new insight on the understanding of the transport mechanism under contacts for different TMDs.

With the understanding of the Schottky barrier FETs, lastly, the flexibility of these 2D materials is utilized to create high performance three-dimensionally stacked multi-channel FETs, from the inspiration of the Si gate-all-around nanosheet structure. A first-ever 3D integrated high performance MoS2 device with two channels on top of each other was designed and fabricated, where the current is doubled with an extra layer of channel. The potential of these novel material to be implemented on the future generations of high-performance devices is demonstrated, shedding light on the prospect for extending the Moore’s Law with proper assistance from new materials.


Degree Type

  • Doctor of Philosophy


  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Joerg Appenzeller

Additional Committee Member 2

Zhihong Chen

Additional Committee Member 3

Sumeet Gupta

Additional Committee Member 4

David Janes

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