Timing Optimization of Path Delays for Testing Small Delay Defects

<p dir="ltr">Recent studies of silent data errors (SDEs) in mega-scale datacenters indicate that SDEs are caused by hardware defects, specifically, small delay defects. These defects may have escaped detection by manufacturing tests applied after fabrication and may induce SDEs during the lifetime of the system because of chip aging or environmental conditions. A small delay defect is detected by a test that propagates a transition through one of the longest paths of the design. Paths are selected by static timing analysis that provides an upper bound on path delays. For complex cells, the differences in propagation delays can be substantial, depending on the input stimuli. Existing test generation procedures do not consider these delay differences after a path is selected. To address this issue, this thesis proposes a new approach to test generation for small delay defects that may escape from currently applied tests, called Timing Verification Test or TVT. TVT is guided by a timing database to select the input stimuli to maximize the dynamic delay of the path, calculated as the delays obtained by the actual input stimuli assigned to the cells along the path. Based on the TVT framework, a novel path selection algorithm is developed to select the dynamically longest paths for the detection of small delay defects. The algorithm adopts an iterative and feedback-driven strategy to dynamically update an initial set of the statically longest paths as test generation is carried out, gradually replacing statically longer paths that yield lower dynamic delays with statically shorter paths that yield higher dynamic delays.</p>