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ULTRATHIN INDIUM-BASED SEMICONDUCTORS FOR BACK-END-OF-LINE LOGIC AND MEMORY APPLICATIONS
As the semiconductor technology pushed to 3 nm node and beyond, more and more effort has been input on the investigation of advanced device structures and package technologies such as gate-all-around, vertical stack, and monolithic 3D etc., as well as innovation of ultrathin materials including van der Waals 2D materials and atomically thin oxide semiconductors. Among them, Back-end-of-line compatible materials and devices for logic and memory have been attracting more and more attention due to the quantifiable performance and energy efficiency advantages application in Monolithic 3-D Integration.
Indium-based compound semiconductors, in the form of either amorphous or crystalline, is an emerging material platform with outstanding electrical and optoelectronic properties. In this dissertation, we will focus on novel Indium-based (In2X3, X= O, Se…) based material system, especially the theoretical investigation and experimental effort from material growth to various device characterizations and applications. Systematic investigation is performed on low-thermal-budget Zn or W-doped In2O3 down to 40 nm channel lengths revealing excellent transistor characteristics including on currents approaching 1.5 A/mm because of unique band alignment, close to the ideal 60 mV/dec subthreshold swing from the high-quality interface, and high on/off ratios of 1012 due to the wide bandgap. Meanwhile, record-high positive-bias-stress stability is achieved by ultrathin Zn-doped In2O3 thin-film transistors with negligible threshold voltage shift (-16 mV) and high-frequency GHz operation enabling perfect alignment with CMOS logic voltages and clock frequencies. Beyond indium oxide, In2Se3 also show excellent semiconductor and ferroelectric features. 3 nm, mm-scale size continuous films can be grown and transferable perfectly to meet the BEOL process temperature requirement and ultrathin van der Waals In2Se3/p+ Si asymmetric ferroelectric semiconductor junctions is fabricated with high current density/distinction ratio targeting next-generation ultra-dense memory applications. A model of the depletion-assisted ferroelectric switch for 2D FE semiconductors is proposed and simulated to explain the presence of ferroelectricity in semiconducting In2Se3.
These works lay out the foundation for hyper-scaling electronic devices with enhanced functionality design in the post-Moore’s law era.
- Doctor of Philosophy
- Electrical and Computer Engineering
- West Lafayette