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<b>ATOMIC LAYER DEPOSITION OF WAFER SCALE TELLURIUM AND TELLURIUM OXIDE FILMS FOR BEOL P-TYPE TRANSISTORS</b>

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posted on 2025-07-25, 01:58 authored by Pukun TanPukun Tan
<p dir="ltr">As Silicon semiconductor downscaling approaches quantum limits, there is a growing demand for alternative materials to enable monolithic three-dimensional (M3D) integration, extending the semiconductor roadmap beyond current CMOS technology. Among these, non-silicon n-type semiconductors—such as oxide semiconductors (e.g., In₂O₃ and IGZO) and chalcogenides (e.g., MoS₂ and CdS)—are promising candidates due to their excellent electrical performance and compatibility with back-end-of-line (BEOL) processes. However, achieving similar scalability and performance in p-type semiconductors remains a challenge. Recently, Tellurium (Te) has emerged as a promising candidate due to its appealing electrical properties and potential low-temperature production. So far nearly all the scalable production and integration of Te with complementary metal oxide semiconductor (CMOS) technology have been based on physical vapor deposition. In this thesis, we demonstrate an advancement with wafer-scale p-type field-effect transistors (FETs) fabricated from an ALD-grown TeOₓ/Te heterostructure. The as deposited film shows wafer-scale uniformity and good electrical performance. Furthermore, a surface accumulation induced good ohmic contact has been observed and explained by the unique band-alignment of the charge neutrality level (CNL) inside the Te valence band. Based on that, we explored its integration in advanced CMOS architectures. We demonstrated complementary FET (CFET) and 2T0C complementary gain cells (CGCs) memory based on ALD Te and IGZO. The CFET inverters we developed show outstanding performance, with a gain of 116.5 V/V and a noise margin of 2.2V (88%) at V<sub>DD</sub> = 5 V. The CGCs show a sub-100 ms write speed with a retention > 10<sup>3</sup> s at room temperature. An ultra retention with 5-bit multilevel operation is demonstrated at low temperature. Our work provides the promise for considering novel ALD channel materials as BEOL-compatible CMOS technologies for monolithic 3D integration.</p><p><br></p>

History

Degree Type

  • Doctor of Philosophy

Department

  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Peide Ye

Additional Committee Member 2

Xianfan Xu

Additional Committee Member 3

Saeed Mohammadi

Additional Committee Member 4

Wenzhuo Wu

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