Device-Circuit Co-Design of Emerging Memory Technologies to Enable Robust and Energy-Efficient In-Memory Computing for Deep Neural Networks

There is an ever-increasing interest in crossbar-enabled in-memory computing (IMC) for deep neural networks and the importance of the design exploration in this area is accentuated by the suitability of various emerging non-volatile memory (NVM) technologies that offer many promising attributes but come with their own overheads. The question is how the unique attributes (both the useful features and non-idealities) affect the system performance and how the designers should choose a technology, its design methodologies and the circuit design techniques. The objective of this work is to address this question by exploring the implications of different technologies for IMC via device-circuit co-design. The first part of the thesis focuses on a promising NVM known as ferroelectric transistors (FeFETs). We analyze the impact of ferroelectric thickness (T_FE) and device-circuits interactions in FeFET-based synaptic crossbar arrays. Our results show that FeFETs with T_FE around 10nm and 7nm achieve the lowest IMC energy and latency and the highest IMC robustness respectively. We also propose a non-volatile Quinary Compute-Enabled Non-Volatile Memory (QeC-NVM) in which cross-coupling of multi-bit FeFET bit-cells is utilized to achieve IMC in the signed quinary regime. Array-level evaluation shows that QeC-NVM achieves lower IMC energy and latency than the baseline 1T-FeFET IMC array. Second, we explore the design space and comparatively evaluate four prominent memory technologies—SRAM, FeFET, ReRAM, and SOT-MRAM with a focus on the IMC robustness in crossbar arrays and the influence of the technologies on DNN inference accuracy. Our results for ResNet-20 with CIFAR-10 show that FeFETs-based IMC achieves the highest accuracy thanks to the high distinguishability and compact bit-cell layout of FeFET. Last, we design and compare digital and analog in-sensor and in-memory computing (ISIMC) macros based on various memory technologies. We evaluate macro-level area, energy and latency of the ISIMC macros and establish the relative pros and cons of different design options.