<b>Emerging Logic and Memory Devices Based On Atomically Thin Oxide Semiconductors</b>

<p dir="ltr">As the fundamental limits of two-dimensional (2D) geometric scaling of commercial transistors are being reached, there is tremendous demand for new materials, innovative device structure and process innovations that can keep delivering performance improvements for future nodes. Meanwhile, the explosive growth of artificial intelligence (AI) is driving the need for memory solutions offering high density, high speed and compact integration with logic circuits. One promising degree is the incorporation of z-dimensional by vertically stacking logic and memory layers with high-density interconnections. This approach requires both logic and memory devices compatible with back-end-of-line (BEOL) and monolithic 3D (M3D) integration.</p><p dir="ltr">A critical prerequisite for BEOL and M3D systems is the strict thermal budget less than 400 °C, which significantly narrows the pool of suitable channel material. Depositing crystalline phase at these temperatures is highly challenging, while polycrystalline phase suffers from grain boundary and instability issues. Amorphous phase, on the other hand, are generally limited by low mobilities. However, amorphous indium oxide (In₂O₃) based metal oxides are exceptions, which features wide bandgap with high electron concentration and mobility over 110 cm²/V∙s, due to a strong surface accumulation with Fermi level (E_F) pinned deeply inside the conduction band (E_C).</p><p dir="ltr">This dissertation explores solutions to BEOL M3D integration at four levels granularity. First, the dissertation comprehensively characterizes and studies the ultra-scaled ALD In₂O₃field effect transistors (FETs) with a channel length (L_ch) of 7 nm and an equivalent oxide thickness below 0.8 nm, achieving a record-high on-state drain current (I_ON) exceeding 10 A/mm. At the second granularity, it investigates solutions toward high-density memory based on ALD In₂O₃ferroelectric FETs (Fe-FETs) with an L_ch of 8 nm with ultra-fast operation. This level includes two investigations: one is significant enhancement of memory and reliability performance by device scaling; another is reliable multi-level-cell operation at cryogenic conditions. At the third granularity, this dissertation demonstrates the enhancement of In₂O₃ field-effect mobility over 150 cm²·v^-1·s^-1 using hafnia-based higher-dielectric-constant (higher-κ) dielectrics. At the fourth level, the dissertation demonstrates a vertical-channel all-oxide “oxidide” platform toward process-material-device co-engineering, focus on vertical-stacked logic and memory with degenerated In₂O₃ sidewallgate and DRAM-process compatibility. This architecture and optimized fabrication process delivers robustness, reliability and high-density arrays with sustainability.</p>