<b>TWO-DIMENSIONAL SEMICONDUCTORS FOR FUTURE TRANSISTORS</b>

<p dir="ltr">Silicon (Si) transistors have long powered modern information technology from personal computing to smartphones and artificial intelligence. Their evolution has been guided by Moore’s Law for over five decades, historically doubling transistor density every two years through relentless scaling and innovation in materials and device structures. Yet even with a 5-nanometer Si body, gate lengths cannot shrink below 10 nanometers without severe short-channel effects. This raises a key question: Can Moore’s Law continue through further scaling, or are we reaching its fundamental limit?</p><p dir="ltr">Two-dimensional (2D) semiconductors, with sub-nanometer thickness and dangling-bond-free surfaces, enable strong electrostatic control at gate lengths below 5 nanometers, approaching the ultimate limit set by source-to-drain direct tunneling. However, these “interface-only” transistors present a different challenge: how to interface them with the three-dimensional (3D) world. As Pauli said, “God made the solids, but the devil their surfaces.”</p><p dir="ltr">First, I will develop a fundamental understanding of 2D nanotransistors using the Landauer formula based on lessons from Professor Datta and Professor Lundstrom. I will discuss the fundamental limits of 2D nanotransistors and the impact of effective mass and equivalent oxide thickness. </p><p dir="ltr">With these fundamental understandings, I will focus on the device physics and technology of 2D transistors, with a particular emphasis on gate stack, doping, and contact engineering. </p><p dir="ltr">For gate stack, I will present our work on n-type monolayer molybdenum disulfide (MoS₂) devices using a tantalum oxide (TaO_x) gate stack and hexagonal boron nitride (hBN) gate stack, achieving near-ideal subthreshold swing and high drive current, along with insights into reliability degradation. I will then introduce a native oxide, tungsten oxide (WO_x) interlayer, for p-type tungsten diselenide (WSe₂) transistors. Such a native oxide interlayer can significantly improve the dielectric-semiconductor interface by reducing hysteresis and improving subthreshold swing. </p><p dir="ltr">I will then discuss how to make a good contact with novel doping technologies. First, I will elucidate the doping mechanism of nitric oxide and present how we combine nitric oxide doping with charge-transfer doping from WO_x and ultrathin dielectrics to achieve high current density and ultralow contact resistance. These results demonstrate that with proper interface design, high-performance and ultrascaled complementary logic based on 2D monolayers becomes viable</p>