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IMPROVING COVERAGE OF CIRCUITS BY USING DIFFERENT FAULT MODELS COMPLEMENTING EACH OTHER

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thesis
posted on 23.07.2021, 15:45 by Oindree BasuOindree Basu

Various fault models such as stuck-at, transition, bridging have been developed to better model possible defects in manufactured chips. However, over the years as device sizes have shrunk, the probability of systematic defects occurring in chips has increased. To predict the sites of occurrence of such defects, Design-for-Manufacturability (DFM) guidelines have been established, the violations of which are modelled into DFM faults. Nonetheless, some faults corresponding to DFM as well as other fault models are undetectable, i.e., tests cannot be generated to detect their presence. It has been seen that undetectable faults usually tend to cluster together, leaving large areas in a circuit uncovered. As a result, defects occurring there, even if detectable, go undetected because there are no tests covering those areas. Hence, this becomes an important issue to address, and to resolve it, we utilize gate- exhaustive faults to cover these areas. Gate-exhaustive faults provide exhaustive coverage to gates. They can detect any defect which is not modelled by any other fault model. However, the total number of gate-exhaustive faults in a circuit can be quite large and may require many test patterns for detection. Therefore, we use procedures to select only those faults which can provide additional coverage to the sites of undetectable faults. We de ne parameters that determine whether a gate associated with one or more undetectable faults is covered or not, depending on the number of detectable and useful gate-exhaustive faults present around the gate. Bridging faults are also added for extra coverage. These procedures applied to benchmark circuits are used for obtaining the experimental results. The results show that the sizes of clusters of undetectable faults are reduced, upon the addition of gate-exhaustive faults to the fault set, both in the case of single-cycle and two-cycle faults.

History

Degree Type

Master of Science in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Campus location

West Lafayette

Advisor/Supervisor/Committee Chair

Irith Pomeranz

Additional Committee Member 2

Anand Raghunathan

Additional Committee Member 3

Cheng-Kok Koh