Influence of Size and Interface Effects of Silicon Nanowire and Nanosheet for Ultra-Scaled Next Generation Transistors

In this work, we investigate the trade-off between scalability and reliability for next generation logic-transistors i.e. Gate-All-Around (GAA)-FET, Multi-Bridge-Channel (MBC)-FET. First, we analyze the electronic properties (i.e. bandgap and

quantum conductance) of ultra-thin silicon (Si) channel i.e. nano-wire and nano-sheet based on first principle simulation. In addition, we study the influence of interface

states (or dangling bonds) at Si-SiO₂ interface. Second, we investigate the impact of bandgap change and interface states on GAA-FETs and MBC-FETs characteristics by

employing Non-equilibrium Green's Function based device simulation. In addition to that, we calculate the activation energy of Si-H bond dissociation at Si-SiO₂ interface for different Si nano-wire/sheet thickness and different oxide electric-field. Utilizing these thickness dependent activation energies for corresponding oxide electric-field, in conjunction with reaction-diffusion model, we compute the characteristics shift and analyze the negative bias temperature instability in GAA-FET and MBC-FET. Based on our analysis, we estimate the operational voltage of these transistors for a life-time of 10 years and the ON current of the device at iso-OFF-current condition. For example, for channel length of 5 nm and thickness < 5 nm the safe operating voltage needs to be < 0.55V. Furthermore, our analysis suggests that the benefit of Si thickness scaling can potentially be suppressed for obtaining a desired life-time of GAA-FET and MBC-FET.